Hierarchical Partitioning

ABSTRACT

Some embodiments provide a method of simulating an electrical circuit that receives a circuit description that has a set of sub-circuits. The method defines several partitions for several sub-circuits. The method then simulates the circuit using the partitioned sub-circuits. In some embodiments, the method ranks the sub-circuits prior to partitioning based on a parent-child relationship that shows how a sub-circuit is instantiated by other sub-circuits. These embodiments partition child sub-circuits first. Some embodiments provide a method of partitioning an electrical circuit that has a set of sub-circuits. For a particular sub-circuit that is instantiated from other sub-circuits, the method duplicates the particular sub-circuit into a first copy and a second copy when one port of the particular sub-circuit is connected to a voltage source in at least one instance and the same port is not connected to a voltage source in at least another instance.

CLAIM OF BENEFIT TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application60/718,487, entitled “Hierarchical Partitioning,” filed Sep. 18, 2005,which is herein incorporated by reference.

FIELD OF THE INVENTION

The present invention is directed to circuit simulation. Moreparticularly, the present invention is directed to partitioning ofcircuits for general-purpose simulation.

BACKGROUND OF THE INVENTION

General-purpose circuit simulators are powerful tools used in electricalcircuit designs to verify circuit design and to simulate circuitbehavior. For instance, in the integrated circuit (IC) design, the highcosts of manufacturing an IC makes it very essential to verify thecircuit behavior prior to manufacturing. Enormous cost savings areachieved by simulating different variations of a circuit's componentvalues prior to manufacturing.

Circuit simulators such as Simulation Program with Integrated Circuits(SPICE) are widely used to verify electrical circuit design. Theseprograms, however, simulate the entire circuit as a single matrix.Simulating the entire circuit requires a significant amount ofprocessing time as the matrix becomes larger even though the matricesrepresenting electrical circuits are very sparse. To reduce processingtime, another group of simulators with less accurate but more efficientalgorithms have been designed. These simulators, referred to as timingsimulators, use simplified device models and equation formulationtechniques. Many of these simulators compute circuit delays bysimulating the response of the circuit to a given set of inputs.

In the past, timing simulators have flatly partitioned the entirecircuit into small groups of transistors, so that they can solve a setof smaller matrices instead of one large matrix. Since the timenecessary to solve a matrix grows super-linearly with respect to thenumber of rows and columns, solving several small matrices can be fasterthan solving a single large matrix. Also, partitioning the circuitallows the simulator to take advantage of latency and to employmulti-rate algorithms in solving the system equations. Flattening acircuit, however, can significantly increase memory consumption. As thesize of modern IC and board level circuits grow, the impact of memoryconsumption becomes more significant. In addition, timing simulators areless accurate than simulators such as SPICE. Hence, there is a need inthe art for a fast and highly-accurate simulator that achieves higherspeed without significantly increasing memory consumption.

SUMMARY OF THE INVENTION

Some embodiments provide a method of simulating an electrical circuit.The method receives a circuit description that has a set ofsub-circuits. The method defines several partitions for severalsub-circuits. Each partition includes a set of devices and deviceterminals. The method then simulates the circuit using the partitionedsub-circuits. In some embodiments, the method ranks the sub-circuitsprior to partitioning based on a parent-child relationship that showshow a sub-circuit is instantiated by other sub-circuits. Theseembodiments partition child sub-circuits first.

Some embodiments provide a method of partitioning an electrical circuit.The method receives a circuit description that includes a set ofsub-circuit descriptions. The method identifies whether a sub-circuit isinstantiated from other sub-circuits. For a particular sub-circuit thatis instantiated from other sub-circuits, the method duplicates theparticular sub-circuit into a first copy and a second copy when one portof the particular sub-circuit is connected to a voltage source in atleast one instance and the same port is not connected to a voltagesource in at least another instance. In some embodiments, the methodreferences the first copy when the particular sub-circuit isinstantiated by another sub-circuit in which the port is connected to avoltage source. The method references the second copy when theparticular sub-circuit is instantiated by another sub-circuit in whichthe port is not connected to a voltage source.

BRIEF DESCRIPTION OF THE DRAWINGS

The novel features of the invention are set forth in the appendedclaims. However, for purpose of explanation, several embodiments of theinvention are set forth in the following figures.

FIG. 1 illustrates a simplified block diagram of the circuit simulatorof some embodiments.

FIG. 2 conceptually illustrates a high level process that hierarchicallypartitions a circuit in some embodiments.

FIG. 3 illustrates a process that partitions a sub-circuit in someembodiments.

FIG. 4 illustrates a process that ranks sub-circuits in someembodiments.

FIG. 5 illustrates a process that performs partitioning of a sub-circuitin some embodiments.

FIG. 6 illustrates a process that groups the devices in someembodiments.

FIGS. 7-10 illustrate grouping terminals for a MOS transistor device insome embodiments.

FIGS. 11-14 illustrate grouping terminals for resistor, diode, inductor,and current source devices in some embodiments.

FIGS. 15-18 illustrate grouping terminals for a capacitor device in someembodiments.

FIGS. 19-21 illustrate grouping terminals for a BJT transistor in someembodiments.

FIG. 22 conceptually illustrates a process that finds all feedback loopsin a sub-circuit in some embodiments.

FIG. 23 conceptually illustrates a process that finds the feedback loopscontaining a node in some embodiments.

FIG. 24 illustrates a process that levelizes nodes of all sub-circuitsin some embodiments.

FIG. 25 illustrates a process that levelizes a node in some embodiments.

FIG. 26 conceptually illustrates a computer system with which someembodiments are implemented.

DETAILED DESCRIPTION OF THE INVENTION

In the following description, numerous details are set forth for purposeof explanation. However, one of ordinary skill in the art will realizethat the invention may be practiced without the use of these specificdetails. In other instances, well-known structures and devices are shownin block diagram form in order not to obscure the description of theinvention with unnecessary detail.

I. Overview of the Circuit Simulator that Uses Hierarchical Partitioning

Some embodiments provide a method of simulating an electrical circuit.The method receives a circuit description that has a set ofsub-circuits. The method defines several partitions for severalsub-circuits. Each partition includes a set of devices and deviceterminals. The method then simulates the circuit using the partitionedsub-circuits. In some embodiments, the method ranks the sub-circuitsprior to partitioning based on a parent-child relationship that showshow a sub-circuit is instantiated by other sub-circuits. Theseembodiments partition child sub-circuits first.

Some embodiments provide a method of partitioning an electrical circuit.The method receives a circuit description that includes a set ofsub-circuit descriptions. The method identifies whether a sub-circuit isinstantiated from other sub-circuits. For a particular sub-circuit thatis instantiated from other sub-circuits, the method duplicates theparticular sub-circuit into a first copy and a second copy when one portof the particular sub-circuit is connected to a voltage source in atleast one instance and the same port is not connected to a voltagesource in at least another instance. In some embodiments, the methodreferences the first copy when the particular sub-circuit isinstantiated by another sub-circuit in which the port is connected to avoltage source. The method references the second copy when theparticular sub-circuit is instantiated by another sub-circuit in whichthe port is not connected to a voltage source.

FIG. 1 illustrates a simplified block diagram of a circuit simulator 100of some embodiments. As shown, the simulator 100 includes a parser 105,a partitioning module 110, and a simulation engine 115. The parser 105receives a description of the circuit elements and their connections asinput. In some embodiments, this description is in a form of a textdescription called a netlist. The netlist defines the circuit as a setof one or more sub-circuits. The parser 110 parsers the netlist andconverts it to an internal representation.

The partitioning module breaks the internal representation of thecircuit into smaller partitions. Some embodiments hierarchicallypartition the circuit in way that each sub-circuit is individuallypartitioned. The simulation engine 115 simulates the electrical circuitusing the partitioned internal representation of the circuit. The resultis generated in the form of one or more output files.

FIG. 2 conceptually illustrates a high level process that partitions acircuit hierarchically. As shown, the process receives (at 205) acircuit description that describes the circuits as a set ofsub-circuits. Each sub-circuit can have several devices in it. Next, theprocess hierarchically partitions the circuit by performing thefollowing operations. At 210, the process ranks the sub-circuits toidentify which sub-circuit instantiates other sub-circuits. Thesub-circuits form a parent-child relationship with the parentsub-circuits instantiating child sub-circuits. In some embodiments, thechild sub-circuits are processed first. In these embodiments, theinstances of the instantiated child sub-circuits can be readilypartitioned within their parent sub-circuits.

At 215, the process groups the devices in each sub-circuit into a set ofpartitions to form a directed graph. Next, the process finds (at 220)the feedback loops within the directed graph. At 225, the process mergesthe partitions that form feedback loops to form an acyclic graph.

Finally, at 230, the process levelizes the acyclic graph by assigning alevel to each partition. This level corresponds to the distance that thegroup of devices and their terminals in a partition have from theprimary inputs to the circuit. This information is used by simulationengine 115 to facilitate simulation of the electrical circuit.

Several more detailed embodiments of the invention are described insections below. Section II describes the overall flow of hierarchicalpartitioning in some embodiments. This discussion is followed by thediscussion in Section III that describes further processing of thepartitioned sub-circuits to remove the feedback loops among them and toidentify the order by which the resulting partitions should be simulatedby the simulation engine. Last, Section IV describes a computer systemthat implements some of the embodiments of the invention.

II. Hierarchical Partitioning

A. Overall Flow of Hierarchical Partitioning

Traditional timing simulators flatten the entire circuit beforepartitioning it into smaller blocks. In other words, traditionalsimulators treat the circuit as a whole and do not partitionsub-circuits separately. The graph theory for circuit partitioning isdiscussed in V. Rao and T. Trick, “Network partitioning and ordering forMOS VLSI Circuits,” IEEE Trans. Computer-Aided Design, vol. CAD-6, no 1,January 1987; and V. Rao, D. Overhauser, I. Hajj, and T. Trick,“Switch-Level Timing Simulation of MOS VLSI circuits,” Boston: KluwerAcademic Publishers, 1988. Both of these documents are incorporatedherein by reference.

In order to keep the memory footprint small, some embodiments of theinvention partition the circuit hierarchically. These embodimentspartition the sub-circuits individually. Since a sub-circuit can only beconnected through its ports, some embodiments only utilize informationabout the ports of a child sub-circuit to partition its instances in aparent sub-circuit. In other words, instances in a sub-circuit can betreated as a black box. Thus, only an abstract view of the sub-circuitis used when partitioning the sub-circuit's corresponding instance inits parents.

As an example of the information that is used about an instance in orderto partition it, a MOS transistor can be considered as a four terminaldevice, or analogously as an instance of a sub-circuit with four ports.When none of the terminals are connected to a voltage source, theterminals form three partitions, namely, source and drain in onepartition, and gate and bulk in two separate partitions. Hence, aninstance can be thought of as an N-terminal device. An instance can bepartitioned when it is known how the terminals are partitioned.

FIG. 3 illustrates a process 300 that hierarchically partitions acircuit in some embodiments. Some embodiments partition all the childsub-circuits first. This allows these embodiments to efficientlygenerate the abstract view of a sub-circuit. As shown, the process ranks(at 305) the sub-circuits such that child sub-circuits appear in thelist before their parents. Some embodiments use a depth first searchalgorithm to determine the ranking. This algorithm is described inSub-Section B below.

Next, the process selects (at 310) the sub-circuit with the highest rank(i.e., the sub-circuit that has no children). Since a sub-circuit canonly be connected through its ports, some embodiments can partition asub-circuit when the port properties are known. Those port propertiesare: (1) port is connected to a voltage source node, and (2) port isconnected to a signal net. In other words, these embodiments have todetermine whether a sub-circuit port is connected to a voltage source ornot. At 315, the process determines whether any port in the sub-circuitis connected to both voltage source and signal nets. In other words, theprocess determines whether the sub-circuit has a port that is connectedto a voltage source in some instances and is not connected to a voltagesource in other instances.

If the process determines that no port in the sub-circuit is connectedto both voltage source and signal nets, the process proceeds to 325which is described below. Otherwise, to simplify the complexity of theprocess, the process makes (at 320) two copies of the sub-circuit.Assume that the two sub-circuits are now s1 and s2. Some embodimentshave all instances of the original sub-circuit that have the portconnected to a voltage source net reference sub-circuit s1 and allothers reference sub-circuit s2. Therefore, the port in s1 is alwaysconnected to a voltage source net and the port in s2 is always connectedto a signal net. Some embodiments make two copies of a sub-circuit foreach one its ports that satisfies the criteria mentioned in operation315 above.

At 325, the process connects voltage sources to ports as necessary. Topartition a sub-circuit without any instances, some embodiments connecta fictitious DC voltage source to each port that has a DC path toground. The other ports are left as is.

The process then partitions (at 330) the sub-circuit. Details ofpartitioning an individual sub-circuit is described in Sub-Section Cbelow. Since child sub-circuits are partitioned before their parentsub-circuits, whenever a sub-circuit instantiates other sub-circuits,the instances of these instantiated child sub-circuits can be readilypartitioned within their parent sub-circuits. These instances aretreated as an N-terminal device, except that the instance itself willnot be assigned to a partition, only its terminals. The rule forgrouping devices that is described in Sub-Section C below would have oneadditional rule for an instance. Namely, for all the terminals in thesame partition, group all the corresponding nets connected to thoseterminals, unless they are voltage source nets.

Next, the process builds (at 335) an abstract view of each sub-circuitto facilitate partitioning of its instances within parent sub-circuits.The port properties that are computed for the abstract view are: (1) aport is a voltage source node from within, (2) a port is stronglyconnected, (3) a port is capacitively connected, (4) two or more portsare partitioned together, (5) one or more ports are fan-out ports, and(6) the level between fan-out ports.

At 340, the process determines whether all sub-circuits are processed.If yes, the process exits. Otherwise, the process selects (at 345) thenext highest ranking sub-circuits that is not partitioned yet andproceeds to 315 that was described above.

After the nets and devices have been grouped together, they can berepresented as a directed graph. The nodes of this directed graphrepresent the nets and devices that have been grouped together. Theedges of the directed graph represent the propagation of the signalsthrough the circuit. The signal flow for MOS transistors is from thegate net partition to the source and drain net partitions. The signalflow for voltage source net partitions is from the voltage source net tothe other partitions. The signal flow for coupling capacitors is fromthe coupling capacitor partition to the other partitions. This directedgraph is further processed as described in Section III below to make itsuitable for use by the simulation engine 115.

The rest of this section describes the details of several steps usedduring hierarchical partitioning described above. Sub-Section Bdescribes ranking of individual sub-circuits prior to partitioning.Sub-Section C describes the details of how an individual sub-circuit ispartitioned.

B. Ranking Sub-Circuits

FIG. 4 illustrates a process 400 that ranks the sub-circuits in someembodiments. This process determines which sub-circuit instantiatesother sub-circuits. The highest ranking sub-circuits are the leaves ofthe graph that do not instantiate any other sub-circuits. As shown, theprocess adds (at 405) the top sub-circuit to a pending list. The topsub-circuit with all of it's sub-circuit instances (and it's instances'instances) represents the whole circuit. The process then sets (at 410)the value of “CurrentRank” to 0.

Next, the process sets (at 415) “N” to the number of sub-circuits in thepending list and sets the counter, “i”, to 0. The process thendetermines (at 420) whether “i” is less than “N”. If not, the processproceeds to 430 which is described below. Otherwise, the process setsthe rank of the i^(th) entry in the pending list to the maximum of therank of the i^(th) entry in the pending list and the value of“CurrentRank”. Next, the process increments the value of “i”. Theprocess then proceeds to 420 which was described above.

At 430, the process determines whether the pending list is empty. Ifyes, the process exits. Otherwise, the process schedules the next set ofsub-circuits to be ranked by appending those sub-circuits to the pendinglist. Let the first sub-circuit in the pending list be called “Ckt”. Theprocess pops (at 435) this sub-circuit from the pending list. Theprocess then adds (at 440) sub-circuits used in “Ckt” to a new pendinglist. The process then increments (at 445) the value of “CurrentRank”.The process then recursively performs (at 450) operations 420 to 450 forthe new pending list.

Some embodiments partition a sub-circuit by grouping together thedevices that are strongly connected. In these embodiments, devices thatare coupled through channels or resistors are considered stronglyconnected while devices that are connected through capacitors areconsidered weakly connected.

FIG. 5 illustrates a process 500 that performs partitioning of asub-circuit in some embodiments. As shown, the process first places (at505) each net in the sub-circuit in a unique partition. Next, theprocess merges (at 510) the partitions for the nets that are connectedtogether through channels and resistors. Finally, the devices are added(at 515) to the partitions of the nets that are not connected to voltagesources (as described below, a MOS transistor is never added to thepartition of its gate or bulk terminals). Each one of these operationsis described in more detail below.

C. Grouping Devices of a Sub-Circuit Together

FIG. 6 illustrates a process 600 that groups the devices in someembodiments. This process, referred to as channel-connected partitioninginitially ensures that each net (a net is a terminal or a connection ona device) is in a unique partition. Nets connected to a DC voltagesource form their own partitions (a voltage source net is any net thathas a path to ground through voltage sources. This includes nets thatare directly connected to ground). The process then examines each deviceby performing the following set of operations.

The process determines (at 605) whether the device is a MOS transistor.If not, the process proceeds to 635 which is described below. Otherwise,the process determines whether neither the source terminal nor the drainterminal of the transistor is connected to a voltage source net. If atleast one terminal is connected to a voltage source net, the processproceeds to 620 which is described below. Otherwise, the process merges(at 615) both net partitions and adds the device to the mergedpartition. The process then exits. This operation is illustrated in FIG.7. Neither the source nor the drain terminal of MOS transistor 700 isconnected to a voltage source net. As shown, process 600 merges thepartitions of the two terminals, “B” and “C”, and adds the device to themerged partition to create partition 705. The gate terminal, “A”, andthe bulk terminal, “D”, remain in separate partition 710 and 715respectively.

At 620, the process determines whether only one of the source or drainterminals is connected to a voltage source. If not, the process proceedsto 630 which is described below. Otherwise, the process adds (at 625)the device to the non voltage-source net partition. This operation isillustrated in FIG. 8. The source terminal of MOS transistor 805 isconnected to a voltage source, VDD. As shown, process 600 adds thedevice to the partition of the drain net, “C” which is not connected tothe voltage source. The voltage source, the gate terminal, and the bulkterminal remain in separate partitions. Similarly, FIG. 9 illustrates aMOS transistor 900 which its drain terminal connected to ground. Asshown, process 600 adds the device to the partition of the source net,“B”, which is not connected to ground. The gate terminal, the bulkterminal, and ground remain in separate partitions.

When the process determines (at 620) that both terminals are connectedto voltage sources, the process creates (at 630) a new partition for thedevice. The process then exits. This operation is illustrated in FIG.10. The source terminal of MOS transistor 1000 is connected to a voltagesource, VDD and the drain terminal is connected to ground. As shown,process 600 creates a new partition 1005 for the device. The gateterminal, the bulk terminal, the voltage source, and ground remain inseparate partitions.

When the process determines (at 605) that the device is not a MOStransistor, the process determines (at 635) whether the device is aresistor, inductor, diode, or current source. If not, the processproceeds to 665 which is described below. Otherwise, the processdetermines (at 640) whether neither terminal is connected to a voltagesource. If at least one terminal is connected to a voltage source, theprocess proceeds to 650 which is described below. Otherwise, the processmerges both net partitions and adds the device to the merged partition.The process then exits. This operation is illustrated in FIG. 11.Neither terminals of device 1100 (which can be a resistor, diode,inductor, or current source) is connected to a voltage source. As shown,process 600 merges both net partitions and adds the device to the mergedpartition 11105.

At 650, the process determines whether only one terminal is connected toa voltage source. If not, the process proceeds to 660 which is describedbelow. Otherwise, the process adds the device to the non-voltage sourcenet partition. This operation is illustrated in FIG. 12. As shown, oneof the terminals is connected to a voltage source, VDD. Process 600 addsthe device to the non-voltage source net partition 1205. The voltagesource remains in a separate partition 1205. Similarly, FIG. 13illustrates a device with one of its terminals connected to ground.Process 600 adds the device to the non voltage-source net partition1305. The ground net remains in a separate partition 1310.

When the process determines (at 650) that both terminals are connectedto voltage sources, the process creates (at 660) a new partition for thedevice. The process then exits. This operation is illustrated in FIG.14. As shown, the two terminals of the device are connected to a voltagesource, VDD, and ground. Process 600 creates a new partition 1405 forthe device. The voltage source and ground remain in separate partitions.

When the process determines (at 635) that the device is not a resistor,inductor, diode, or current source, the process determines (at 665)whether the device is a capacitor. If not, the process proceeds to 682which is described below. Otherwise, the process determines (at 670)whether none of the terminals are connected to a voltage source net orboth terminals are connected to voltage sources. If only one terminal isconnected to a voltage source, the process proceeds to 680 which isdescribed below. Otherwise, the process creates (at 675) a new partitionfor the device. The process then exits. This operation is illustrated inFIG. 15. As shown, none of the terminals of capacitor 1500 is connectedto a voltage source. Process 600 creates a new partition 1505 for thedevice. Similarly, FIG. 16 illustrates a capacitor 1600 which oneterminal connected to a voltage source, VDD, and the other terminalconnected to ground. Process 600 creates a new partition 1600 for thedevice.

When the process determines (at 670) that only one terminal is connectedto a voltage source, the process adds (at 660) the device to the nonvoltage-source net partition. The process then exits. This operation isillustrated in FIG. 17. As shown, one of the terminals of capacitor 1700is connected to a voltage source, VDD. Process 600 adds the device tothe non voltage-source net partition 1705. Similarly, FIG. 18illustrates a capacitor 1800 with one of its terminals connected toground. Process 600 adds the device to the non voltage-source netpartition 1805.

When the process determines (at 665) that the device is not a capacitor,the process determines (at 682) whether the device is a voltage source.If yes, the process creates a new partition for the device. The processthen exits. Otherwise, the process determines (at 686) whether thedevice is a BJT transistor. If not, the process exits. Otherwise, theprocess determines whether none of the base, collector, and emitterterminals are connected to a voltage source. If not, the processproceeds to 692 which is described below.

Otherwise, the process merges (at 690) all net partitions and adds thedevice to the merged partition. The process then exits. This operationis illustrated in FIG. 19. As shown, process 600 merges all netpartitions and adds the device to the merged partition 1905.

At 692, the process determines whether all terminals are connected tovoltage sources. If not, the process proceeds to 696 which is describedbelow. Otherwise, the process creates a new partition for the device.The process then exits. This operation is illustrated in FIG. 20. Asshown all terminals of transistor 2000 are connected to voltage sources.Process 600 creates a new partition 2005 for the device. All terminalsremain in separate partitions.

When the process determines (at 692) that some (but not all) terminalsare connected to voltage sources, the process merges (at 696) the nonvoltage-source nets. The process then adds the device to the mergedpartition. The process then exits. This operation is illustrated in FIG.21. As shown, one of the terminals is connected to ground. Process 600merges the non voltage-source net partitions and adds the device to themerged partition 2105.

III. Further Processing of the Directed Graph after IndividualSub-Circuits are Partitioned

After the directed graph is generated using the process described inSection II above, the directed graph is further processed to remove itsfeedback loops and to identify the order in which the partitions shouldbe simulated by the simulation engine 115.

A. Finding Feedback Loops

Next, the feedback loops of the directed graph are identified. Feedbackloops are the set of nodes and edges, such that for two nodes w and v,there is a path from w to v and a path from v to w. To find the feedbackloops, some embodiments determine the fan-out relationship of theinstance terminals. Each instance terminal corresponds to a sub-circuitport. This port belongs to a partition. Port P2 is a fan-out of Port P1,if there exists a path from the partition containing port P1 to thepartition containing Port P2. This can be computed once, after thesub-circuit is partitioned.

Some embodiments then apply Tarjan's algorithm to find feedback loops ina sub-circuit. Tarjan's Algorithm (described in R. Tarjan, “Depth-firstsearch and linear graph algorithms,” SIAM J. Comput., vol. 1, no. 2, pp.146-160, June 1972) is an efficient method for finding the loops in thedirected graph. Tarjan's Algorithm is described in R. Tarjan,“Depth-first search and linear graph algorithms,” SIAM J. Comput., vol.1, no. 2, pp. 146-160, June 1972. This paper is incorporated herein byreference.

FIG. 22 illustrates a process 2200 that processes a graph to identifyits feedback loops. The process initially sets (at 2205) a flag, n, to0. This flag has two purposes. The first purpose is to assign a uniqueloop identifier to each node while the graph is processed. The secondpurpose is to uniquely identify the order the node has been processed.Next, the process determines (at 2210) whether all nodes of the graphare processed. If yes, the process exits. Otherwise, the process finds(at 2215) the feedback loop for the next unprocessed node, v. Findingthe feedback loop for a node is described in FIG. 23.

FIG. 23 illustrates a process 2300 that determines if a node (i.e., apartition) is in a feedback loop. As shown, initially the loopidentifier, “L”, of node v is set to n. Also, node processing order,“K”, is set to n. The node processing order, “K”, is used by process2300 to determine if there is a feedback loop for node v. It also allowsthe process to efficiently determine all the nodes that belong to thesame feedback loop.

Next, the process increments (at 2310) the value of n. Next the processmarks (at 2315) node v as processed. The process then pushes (at 2320)node v into a stack. The process then puts (at 2325) all fan-out nodesof node v into a set. Next, the process determines (at 2330) whether thefan-out set is empty. If yes, the process proceeds to 2365 which isdescribed below. Otherwise, the process removes one of the fan-outnodes, w, from the set.

Next, the process determines (at 2340) whether node w has beenprocessed. If yes, the process proceeds to 2355 which is describedbelow. Otherwise, the process recursively finds (at 2345) feedback loopsthat contain node w. The process then sets (at 2350) the loop identifierof node v (L[v]) to the minimum of the current loop identifier of node vand the loop identifier of node w. If node v and node w are in differentloops, this step effectively merges both loops into a single loopcontaining both node v and node w. The process then proceeds to 2330which was described above.

When the process determines (at 2340) that node w has been alreadyprocessed, the process determines (at 2355) whether K[w] is less thanK[v] and whether node w is on the stack. If not, the process proceeds to2330 which was described above. Otherwise, the process sets the level ofnode v (L[v]) to K[w].

When the process determines (at 2330) that the fan-out set of node v isempty (i.e., all fan-out nodes are already processed), the processdetermines (at 2365) whether the level of node v (L[v]) is equal toK[v]. If not, the process exits. Otherwise, the process determines (at2370) whether node v is on the stack. If not, the process exits.Otherwise, the process pops (at 2375) the stack into node w. Next, theprocess adds node w to node v's feedback loop. The process then proceedsto 2365 which was described above.

B. Removing Feedback Loops

After the feedback loops have been determined, some embodiments mergethe nodes that form feedback loops to form an acyclic graph. Thisacyclic graph is suitable for the simulation engine 115 to process. Asimple depth first search algorithm is then used (as described below) todetermine the levels of each node in the acyclic graph.

C. Levelizing Node and Device Groups

Determining the levels of each node in the acyclic graph identifies theorder in which the partitions should be simulated by the simulationengine 115. The nodes in the acyclic graph can then be assigned a levelrepresenting the depth of the node in the graph. This corresponds to thedistance that the group of nets and devices are from the primary inputsto the circuit. Nodes that have no fan-ins are assigned level 0. Thesenodes are the partitions that represent the primary inputs. The level ofa node is one more than the maximum level of all of its fan-ins.

Some embodiments also use levelization of the circuit hierarchically.Computing a level for a node informs the simulator the order in which apartition should be processed. While in a flat circuit each node can bethought of as having a weight of one, in the hierarchical case, theinstance terminals can have a weight greater than one. Specifically, theweight of each instance terminal is equal to the level of all itschildren. FIG. 24 illustrates a process 2400 that levelizes a circuit insome embodiments. As shown, the process determines (at 2405) whether allsub-circuits are processed. If yes, the process exits. Otherwise, theprocess merges (at 2410) nodes in the same feedback loop to form anacyclic graph.

Next, the process adds (at 2415) the root node in the graph to a list.The root node represents the entire feedback group in the graph. Theprocess then determines whether all nodes in the list are processed. Ifyes, the process proceeds to 2405 which was described above. Otherwise,the process levelizes the next unprocessed node as described inconjunction with FIG. 25 below. The process then proceeds to 2420 whichwas described above.

FIG. 25 illustrates a process 2500 that levelizes a node in someembodiments. As shown, the process determines (at 2505) whether the nodehas any fan-in nodes. If no, the process proceeds to 2525 which isdescribed below. Otherwise, the process determines (at 2510) whether allfan-in nodes have been processed. If yes, the process proceeds to 2520which is described below. Otherwise, the process recursively levelizesthe unprocessed fan-in. The process then proceeds to 2510 which wasdescribed above.

At 2520, the process calculates the value of “fan-in weight+fan-inlevel+1” for each fan-in of the node and sets the node level to themaximum of these computed values. The fan-in level is an indication ofhow deep a partition is embedded within other sub-circuits. The fan-inweight is the effective level of the node. After 2520, the processexits.

When the process determines (at 2505) that the node does not havefan-ins, the process assigns (at 2525) the node to level 0. The processthen adds (at 2530) the node fan-outs to the list. The process thenexits.

IV. Computer System

FIG. 26 conceptually illustrates a computer system with which someembodiments of the invention are implemented. The computer system 2600includes a bus 2605, a processor 2610, a system memory 2615, a read-onlymemory 2620, a permanent storage device 2625, input devices 2630, andoutput devices 2635.

The bus 2605 collectively represents all system, peripheral, and chipsetbuses that support communication among internal devices of the computersystem 2600. For instance, the bus 2605 communicatively connects theprocessor 2610 with the read-only memory 2620, the system memory 2615,and the permanent storage device 2625.

From these various memory units, the processor 2610 retrievesinstructions to execute and data to process in order to execute theprocesses of the invention. The read-only-memory (ROM) 2620 storesstatic data and instructions that are needed by the processor 2610 andother modules of the computer system. The permanent storage device 2625,on the other hand, is a read-and-write memory device. This device is anon-volatile memory unit that stores instruction and data even when thecomputer system 2600 is off. Some embodiments of the invention use amass-storage device (such as a magnetic or optical disk and itscorresponding disk drive) as the permanent storage device 2625. Otherembodiments use a removable storage device (such as a floppy disk orzip® disk, and its corresponding disk drive) as the permanent storagedevice.

Like the permanent storage device 2625, the system memory 2615 is aread-and-write memory device. However, unlike storage device 2625, thesystem memory is a volatile read-and-write memory, such as a randomaccess memory. The system memory stores some of the instructions anddata that the processor needs at runtime.

Instructions and/or data needed to perform processes of some embodimentsare stored in the system memory 2615, the permanent storage device 2625,the read-only memory 2620, or any combination of the three. For example,the various memory units may contain instructions for processingmultimedia items in accordance with some embodiments. From these variousmemory units, the processor 2610 retrieves instructions to execute anddata to process in order to execute the processes of some embodiments.

The bus 2605 also connects to the input and output devices 2630 and2635. The input devices enable the user to communicate information andselect commands to the computer system. The input devices 2630 includealphanumeric keyboards and cursor-controllers. The output devices 2635display images generated by the computer system. For instance, thesedevices display IC design layouts. The output devices include printersand display devices, such as cathode ray tubes (CRT) or liquid crystaldisplays (LCD).

Finally, as shown in FIG. 26, bus 2605 also couples computer 2600 to anetwork 2665 through a network adapter (not shown). In this manner, thecomputer can be a part of a network of computers (such as a local areanetwork (“LAN”), a wide area network (“WAN”), or an Intranet) or anetwork of networks (such as the Internet). Any or all of the componentsof computer system 2600 may be used in conjunction with the invention.However, one of ordinary skill in the art will appreciate that any othersystem configuration may also be used in conjunction with the invention.

While the invention has been described with reference to numerousspecific details, one of ordinary skill in the art will recognize thatthe invention can be embodied in other specific forms without departingfrom the spirit of the invention. In other places, various changes maybe made, and equivalents may be substituted for elements describedwithout departing from the true scope of the present invention. Thus,one of ordinary skill in the art would understand that the invention isnot limited by the foregoing illustrative details, but rather is to bedefined by the appended claims.

1-6. (canceled)
 7. A method of partitioning an electrical circuit, themethod comprising: a. receiving a circuit description comprising a setof sub-circuit descriptions; b. identifying whether a sub-circuit isinstantiated from other sub-circuits; and c. for a particularsub-circuit that is instantiated from other sub-circuits, duplicatingthe particular sub-circuit into a first copy and a second copy when oneport of the particular sub-circuit is connected to a voltage source inat least one instance and the same port is not connected to a voltagesource in at least another instance.
 8. The method of claim 7 furthercomprising: a. referencing the first copy when the particularsub-circuit is instantiated by another sub-circuit in which said port isconnected to a voltage source; and b. referencing the second copy whenthe particular sub-circuit is instantiated by another sub-circuit inwhich said port is not connected to a voltage source. 9-16. (canceled)